The present invention generally relates to an analog switch circuit, and particularly to a semiconductor analog switch circuit having the function of controlling transfer of an analog signal.
An analog switch circuit for controlling an analog signal by a digital signal is widely used in a variety of systems. Currently, it is desired to present an analog switch of high speed, high breakdown voltage and high precision.
A conventional analog switch circuit is illustrated in FIG. 1A. Referring to FIG. 1A, an ON/OFF control (a sample and hold operation) for an analog signal is carried out by a single transistor T1 of a metal oxide semiconductor transistor (MOS transistor) or a junction field-effect transistor (JFET). The transistor T1 is controlled by a clock signal CK supplied from an external circuit. An example of the clock signal CK is illustrated in FIG. 1B. In ideal switching operation, signals appearing at an input terminal IN and an output terminal OUT change as shown in FIG. 1C in response to the clock signal CK. Actually, as shown in FIG. 2, a charge (an electron for the illustrated case) existing in a channel of the transistor T1 in ON state (channel charge), flows out and is injected into circuits provided on both sides of the transistor T1. This is called "clock feed through phenomenon".
The clock feed through phenomenon causes the following undesirable operation. As is shown in FIG. 1A, a load C consisting of only a capacitive element is connected to the output terminal OUT and the drain of the transistor T1. The charge due to the clock feed through phenomenon is injected into the capacitive load C. The injected charge is added to a charge which is previously injected into the capacitive load C from a signal source Ns, and causes an offset in the voltage derived from the charge stored in the capacitive load C, as shown in FIG. 1D. A transistor T2 is provided in order to prevent the occurrence of the offset. The transistor T2 has a gate area approximately half that of the transistor T1 and is of a conduction type identical to that of the transistor T1. The drain and source of the transistor T2 are mutually connected. The transistor T2 is controlled by an inverter INV, which inverts the clock signal CK. When the transistor T1 is turned OFF, the channel charge flows out on both the sides thereof half and half. At this time, the transistor T2 is turned ON and absorbs the channel charge in a channel formed under the gate thereof.
Actually, however, conditions such as impedance on both the sides of the transistor T1 are not the same as each other. For this reason, the amount of charge occurring on one side of the transistor T1 is not identical to the amount of charge occurring on the other side thereof. Therefore, generally, all the charge flowing out of the transistor T1 is not absorbed into the channel of the transistor T2. As a result, it is impossible to effectively prevent the occurrence of the offset. Analog switch circuits similar to the circuit of FIG. 1A are disclosed in Japanese Laid-Open Patent Application Nos. 60-90425 and 63-50208, for example.
It is required to reduce the gate-channel capacitance of the transistor T1 in order to suppress the clock feed through. This can be done by forming a thick gate insulating layer of the MOS transistor forming the transistor T1 or by forming a narrow channel width thereof. However, the above increases ON resistance of the transistor T1. Alternatively, it is possible to reduce the channel length of the transistor T1. However, in the alternative, the breakdown voltage of the transistor T1 decreases. It can be seen from the above description that currently there is no effective solution for reducing the offset due to the occurrence of the clock feed through. Therefore, it is desired to overcome the above-mentioned disadvantages and present an analog switch circuit of high speed, high breakdown voltage and high precision.